2014-10-20 IPCC Intel Xeon Phi Coprocessor Workshop (HMIC1W14)

Date:	October 20 - 21, 2014 9:30 - 17:30
Location:	LRZ Building, Garching/Munich, Boltzmannstr. 1
Contents:	This workshop is part of the LRZ activities as an Intel Parallel Computing Center(IPCC) and it is organized together with Intel. Objective of this workshop is to learn and discuss advanced Xeon Phi™ programming and analysis methodologies. Case Studies of real world codes will be presented as hints for planning the optimal strategy of Xeon Phi ™ Coprocessor usage. The following items serve as suggestions for workshop content. Analysis tools should be applied to IPCC codes. Intel engineers will be available supporting this effort. Some base information will be given before each lab session as a startup. Xeon Phi™ Coprocessor Architecture Xeon Phi™ Coprocessor Software Infrastructure and Programming ( Vectorization, OpenMP, Offloading) Intel MPI best practices for native, symmetric usage and in combination with offloading Intel Trace Analyzer and Collector (ITAC) visualize and profile Intel MPI VTune™ Amplifier XE for advanced sequential and threading analysis e.g. Vectorization analysis Debugging for Xeon Phi™ Case Study for symmetric MPI Case Study for Offload in combination with MPI on the host only Emphasis of this workshop will be “hands on” the IPCC codes. Basic knowledge of Xeon Phi™ programming concepts should be available. A potential procedure is to have 45 minutes of lectures followed by 2 hours of labs. We may also split the audience into groups of different topics.
Prerequisites	This is an advanced level course. The applicants should have good knowledge about MPI, Intel compilers and also some working experience with the Intel MIC architecture.
Language:	English
Teachers:	Intel Representatives
Registration:	Please send your request to Anupam Karmakar (Email: karmakar_at_lrz.de) till October 12, 2014 with Subject: Course HMIC1W14. The number of participants is limited to 6 and offered on a first come, first served basis.