2014-04-28 PRACE PATC Course: Intel MIC&GPU Programming Workshop (HPGU1W13)
| provisional Date: | Monday, April 28 - Wednesday, April 30, 2014, 9:00-18:00 |
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| Location: | LRZ Building, University campus Garching, near Munich |
| Contents: | With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. Particularly GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Beyond introducing the basics of GPGPU-porogramming, we mainly present OpenACC as an easier way to program GPUs using OpenMP-like pragmas. Recently Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. In the beginning of 2013, the first production-level cards named Intel Xeon Phi came on the market. The course discusses various programming techniques for Intel Xeon Phi and includes several hands-on sessions. The course is developed in collaboration with the Erlangen Regional Computing Centre (RRZE) within KONWIHR. Each day is comprised of approximately 5 hours of lectures and 2 hours of hands-on sessions. Tentative program: Day 1: GPGPU & MIC Programming Techniques
Day 2: Basic MIC Programming Methods
Day 3: Advanced MIC Programming
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| Prerequisites | Good working knowledge of at least one of the standard HPC languages: Fortran 95, C or C++. Basic OpenMP and MPI knowledge useful. |
| Language: | English |
| Teachers: | M. Allalen, V. Weinberg (LRZ), J. Treibig (RRZE), M. Klemm (Intel) |
| Registration: | Via the LRZ registration form (Please choose course HPGU1W13) |