This video shows the creation of FPGA Bitfiles for the NI cRIOs.


Since some NI cRIO cards cards are not supported in the Scan Engine and EtherCat custom device, FPGA bitfiles have to be generated to read those cards.


The bitfiles have to be downloaded onto the cRIO in VeriStand. This effects all other projects as well, so please inform other projects/branches if you change the bitfile!


Bitfiles can be changed in the System Explorer unter 'User Variables' by clicking at 'Select/Change FPGA Bitfile' when the target is not used and you are in the same network:


The FPGA bitfiles can be created with the cRIOFPGA.lvproj file and are prepared for the different cRIOs currently used in the laboratory.

  • To add a new cRIO (e.g. NI 9145), go to the Project Explorer, right click on the EtherCAT Master (= Industrial Controller), go to 'New' → 'Targets and Devices' and select the target:

     
  • Adding a new card to the FPGA bitfile:
    • Add 'User-Defined Variables' with the correct name (red), Data Type (blue) and Direction (green - read: FPGA to Host, write: Host to FGPA) and uncheck 'Enable Network Publishing' (orange)

      See the different signal types here: User Defined Variables
       
    • Add the card to the FPGA Target:

       
    • Configure the properties according to how the card should be used:
  • Create a VI to connect the signals from the cards with the user defined variables, data operations on the FPGA can be done
     
  • Create a FPGA Bitfile
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