The control model is structured as follows:
- The PID gains are parameters of the models. Due to limitations in VeriStand, they are transferred as an array and split into the individual parts.
- All input signals to the control are separate for each element:
- read / calc - input signals from the testbed
- fromLogic - input signals from the user / control interface
- The control logic is separate for each module.
When creating or changing the control logic for individual components, it's best program them in the VeriStand interface, see Control code template.
To use the Control code template, the control logic (3) should have one case, where the input signals are routed through:
